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authorTobias Powalowski <tobias@T-POWA-LX.(none)>2009-12-26 09:10:43 +0100
committerTobias Powalowski <tobias@T-POWA-LX.(none)>2009-12-26 09:10:43 +0100
commit352bf98a8ba4a0595d5f5b8c454d47e5e3b9bb09 (patch)
treebe9fff86d689ef8a2152cc5f954c25099cd99632 /patches
parent5efe25e85e3b6e23101da61bdfdb1f755bcb364f (diff)
added intel fix
Diffstat (limited to 'patches')
-rw-r--r--patches/revert-powermanagement-intel-2.6.32.patch157
1 files changed, 157 insertions, 0 deletions
diff --git a/patches/revert-powermanagement-intel-2.6.32.patch b/patches/revert-powermanagement-intel-2.6.32.patch
new file mode 100644
index 0000000..2bf4a7e
--- /dev/null
+++ b/patches/revert-powermanagement-intel-2.6.32.patch
@@ -0,0 +1,157 @@
+--- linux-2.6.32/drivers/gpu/drm/i915/intel_display.c~ 2009-12-03 04:51:21.000000000 +0100
++++ linux-2.6.32/drivers/gpu/drm/i915/intel_display.c 2009-12-26 08:15:21.000000000 +0100
+@@ -3665,125 +3665,6 @@
+ queue_work(dev_priv->wq, &dev_priv->idle_work);
+ }
+
+-void intel_increase_renderclock(struct drm_device *dev, bool schedule)
+-{
+- drm_i915_private_t *dev_priv = dev->dev_private;
+-
+- if (IS_IGDNG(dev))
+- return;
+-
+- if (!dev_priv->render_reclock_avail) {
+- DRM_DEBUG("not reclocking render clock\n");
+- return;
+- }
+-
+- /* Restore render clock frequency to original value */
+- if (IS_G4X(dev) || IS_I9XX(dev))
+- pci_write_config_word(dev->pdev, GCFGC, dev_priv->orig_clock);
+- else if (IS_I85X(dev))
+- pci_write_config_word(dev->pdev, HPLLCC, dev_priv->orig_clock);
+- DRM_DEBUG("increasing render clock frequency\n");
+-
+- /* Schedule downclock */
+- if (schedule)
+- mod_timer(&dev_priv->idle_timer, jiffies +
+- msecs_to_jiffies(GPU_IDLE_TIMEOUT));
+-}
+-
+-void intel_decrease_renderclock(struct drm_device *dev)
+-{
+- drm_i915_private_t *dev_priv = dev->dev_private;
+-
+- if (IS_IGDNG(dev))
+- return;
+-
+- if (!dev_priv->render_reclock_avail) {
+- DRM_DEBUG("not reclocking render clock\n");
+- return;
+- }
+-
+- if (IS_G4X(dev)) {
+- u16 gcfgc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+-
+- /* Down to minimum... */
+- gcfgc &= ~GM45_GC_RENDER_CLOCK_MASK;
+- gcfgc |= GM45_GC_RENDER_CLOCK_266_MHZ;
+-
+- pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+- } else if (IS_I965G(dev)) {
+- u16 gcfgc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+-
+- /* Down to minimum... */
+- gcfgc &= ~I965_GC_RENDER_CLOCK_MASK;
+- gcfgc |= I965_GC_RENDER_CLOCK_267_MHZ;
+-
+- pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+- } else if (IS_I945G(dev) || IS_I945GM(dev)) {
+- u16 gcfgc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+-
+- /* Down to minimum... */
+- gcfgc &= ~I945_GC_RENDER_CLOCK_MASK;
+- gcfgc |= I945_GC_RENDER_CLOCK_166_MHZ;
+-
+- pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+- } else if (IS_I915G(dev)) {
+- u16 gcfgc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+-
+- /* Down to minimum... */
+- gcfgc &= ~I915_GC_RENDER_CLOCK_MASK;
+- gcfgc |= I915_GC_RENDER_CLOCK_166_MHZ;
+-
+- pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+- } else if (IS_I85X(dev)) {
+- u16 hpllcc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, HPLLCC, &hpllcc);
+-
+- /* Up to maximum... */
+- hpllcc &= ~GC_CLOCK_CONTROL_MASK;
+- hpllcc |= GC_CLOCK_133_200;
+-
+- pci_write_config_word(dev->pdev, HPLLCC, hpllcc);
+- }
+- DRM_DEBUG("decreasing render clock frequency\n");
+-}
+-
+-/* Note that no increase function is needed for this - increase_renderclock()
+- * will also rewrite these bits
+- */
+-void intel_decrease_displayclock(struct drm_device *dev)
+-{
+- if (IS_IGDNG(dev))
+- return;
+-
+- if (IS_I945G(dev) || IS_I945GM(dev) || IS_I915G(dev) ||
+- IS_I915GM(dev)) {
+- u16 gcfgc;
+-
+- /* Adjust render clock... */
+- pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
+-
+- /* Down to minimum... */
+- gcfgc &= ~0xf0;
+- gcfgc |= 0x80;
+-
+- pci_write_config_word(dev->pdev, GCFGC, gcfgc);
+- }
+-}
+-
+ #define CRTC_IDLE_TIMEOUT 1000 /* ms */
+
+ static void intel_crtc_idle_timer(unsigned long arg)
+@@ -3897,12 +3778,6 @@
+
+ mutex_lock(&dev->struct_mutex);
+
+- /* GPU isn't processing, downclock it. */
+- if (!dev_priv->busy) {
+- intel_decrease_renderclock(dev);
+- intel_decrease_displayclock(dev);
+- }
+-
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ /* Skip inactive CRTCs */
+ if (!crtc->fb)
+@@ -3937,7 +3812,6 @@
+ return;
+
+ dev_priv->busy = true;
+- intel_increase_renderclock(dev, true);
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+ if (!crtc->fb)
+@@ -4442,7 +4316,6 @@
+ del_timer_sync(&intel_crtc->idle_timer);
+ }
+
+- intel_increase_renderclock(dev, false);
+ del_timer_sync(&dev_priv->idle_timer);
+
+ mutex_unlock(&dev->struct_mutex);